Answered step by step
Verified Expert Solution
Link Copied!

Question

1 Approved Answer

Q) Circle the correct choice in the following: This takes care of scheduling and synchronization between multiple processors Control unit Hardwired Control Operating System All

Q) Circle the correct choice in the following:

This takes care of scheduling and synchronization between multiple processors

Control unit

Hardwired Control

Operating System

All of the above

Compared the CISC, RISC architecture has

Simpler opcode

Simple addressing modes

Fewer load/store

All of the above

The number of instruction types available in the CISC architecture makes the program, a) Smaller

Longer

Does not change

None of the above

Storage space that has the fastest access time

Cache

Main Memory

Hard drive

Registers

Split caches indicate separate

L1 and L2 cache

L2 and L3 cache

Data and Instruction cache

None of the above

In pipelining there is a requirement of this between stages

Memory

Registers

Buffer

None of the above

The main difference(s) between (BSA add) instruction that found in Basic computer and interrupt service routine is:

The location of storing the return address.

The time that must jump to the routine.

The return method to the main program.

a and b.

No one of the above.

If Register R which has (C7)h is shifted arithmetic right then its content will be:

(8E)h

(E3)h

(63)h

No one of the above.

If each memory access time = 2 msec. (and any other time is neglected) and the content of Ac= (7400)h then the time required to execute the following program that found in memory of basic computer is:

6 msec. SPA

10 msec. ADD @ 300

12 msec. INR

8 msec. HLT

No one of the above.

The list of memory instructions is different from the list of I/O in:

Memory-mapped programmed I/O

Isolated programmed I/O

a and b.

No one of the above

The INR control signal for PC register for the following system that consists of (AR, DR, PC, Ac) registers and each one consists of 4 bits and has three control signals (CLR, INR, Load):

T1 x: Ac PC, M[AR] DR

T3 y: Ac Ac + DR, PC PC+1, AR AR + 1

T0 z: DR M[AR], IF Ac=(FF)h then PC PC+1

T2 x: M[AR] PC , Ac 0

T3 y

(T3 y) (T0 z)

(T3 y) (T0 z)

(T3 y) ((T0 z) Ac =(FF)h)

(T3 y) ((T0 z) Ac =(FF)h)

No one of the above.

For the system described in point (11), the RD signal for M is:

T0 z

(T1 x) (T2 x)

(T1 x) (T2 x)

No one of the above.

Step by Step Solution

There are 3 Steps involved in it

Step: 1

blur-text-image

Get Instant Access to Expert-Tailored Solutions

See step-by-step solutions with expert insights and AI powered tools for academic success

Step: 2

blur-text-image

Step: 3

blur-text-image

Ace Your Homework with AI

Get the answers you need in no time with our AI-driven, step-by-step assistance

Get Started

Recommended Textbook for

Modern Database Management

Authors: Jeffrey A. Hoffer Fred R. McFadden

4th Edition

0805360476, 978-0805360479

More Books

Students also viewed these Databases questions