Q. Compare and contrast Ripple-Carry Adder and Carry-Look ahead Adder

1) In a 4-bit ripple-carry adder as shown in Figure 5.2, assume that each full-adder is implemented using the design as shown in Figure 3.11 (a) and each single logic gate (e.g., AND, OR, XOR, etc.) has a propagation delay of 10 ns. What is the earliest time this 4-bit ripple-carry adder can be sure of having a valid summation output? Explain how you reached your answer and how you did your calculations.

2) In a 16-bit ripple-carry adder as shown in Figure 5.2, what is the earliest time this 16-bit ripple-carry adder can be sure of having a valid summation output? Explain how you reached your answer and how you did your calculations.

3) In a 4-bit carry-look-ahead adder using a carry-look-ahead circuit as shown in Figure 5.4, assume the same gate delays as in (2). What is the earliest time this 4-bit carry-look-ahead adder can be sure of a valid summation output? Explain how you reached your answer and how you did your calculations.

5.2 Parallel Fast Adders 14 FA. FA. FA On- i-1 A1 B1 Ao Bo Ai Bi An-1 Bn-1 Figure 5.2 Block diagram of an n-bit ripple-carry adder