Q: We have a direct-mapped cache with 8 locations and data memory with 16 locations. List the mapping of data memory locations to cache locations.

Q: Find the AMAT for a processor with a 2 ns clock cycle time, a miss penalty of 16 clock cycles, a miss rate of 0.02 misses per instruction, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.