Q1) Assume the following register file and memory state in a processor. All values are in hex.

Register File (registers t0-t7 shown):

t0: 0x000000CD

t1: 0x00000338

t2: 0x45454545

t3: 0x00310000

t4: 0x00000428

t5: 0x00001010

t6: 0x2AAAAAAF

t7: 0xFFFFFFFF

Memory:

Address	Data
...
0x0420	40 32 EB CE
0x0424	23 01 DC BE
0x0428	0F F1 CE 04
0x042C	4E 9F FF 54
0x0430	F0 00 00 0D
0x0434	AA F6 98 01
0x0438	00 74 12 00
0x043C	CA FE 00 00
0x0440	FA CE 55 10
...

Describe the contents of register file and memory when the following instructions are executed. Show the changed contents after each instruction. The offsets in load and store instructions are in decimal.

lw, $t2, 16($t4) add, $t6, $t2, $t0 sw, $t6, 8($t4)

Q2) List the source registers and destination registers in the following MIPS instructions. Recall that a source register is read during the instruction's execution, while a destination register is written during the instruction's execution.

Instructions	Source Registers	Destination Registers
and $s1, $s2, $s3
or $t3, $t3, $t3
addi $t3, $zero, 300
lw $t2, 36($t1)
sw $s2, 12($s4)
bne $t1, $t2, LABEL

Q3) Convert the following MIPS instruction andi $s6, $s7, 0x1EA2 to machine code (in both binary and hexadecimal format). Consult the reference sheet uploaded on Blackboard.

Q4) If the bit pattern 0x2A110060 is placed into the instruction register, what MIPS instruction would be executed? Consult the reference sheet uploaded on Blackboard.

Q5) Provide the instruction type (format), assembly language instruction, and binary representation of the two MIPS instructions described by the fields shown below. Consult the reference sheet uploaded on Blackboard.

Instruction 1: op=0x0, Rs=9, Rt=11, Rd=15, shamt =0, funct = 0x25 Instruction 2: op=0x23, Rs=16, Rt=17, immediate=0x8

Q6) Assume that we want to expand the MIPS register file to 128 registers (from current 32 registers). How would this effect the size of each field in the R-type format?