Q1. Below we give an argument to show that the interrupt mechanism (cpu hardware + service routine actions) does not work correctly. Do you agree with the argument? If not, then what is wrong with the argument?

The argument:

Suppose we have a user program fragment:

L1: CMP R1, R2

L2: Jmpn L3

L3:

Now suppose there is a hardware interrupt after executing L1 instruction. Suppose that service routine changes condition codes. So when we come back to execute L2, the Jmpn will not work correctly.

Q2. Suppose all mode bits in PSW item in the Interrupt Vector are USER MODE. What can go wrong when a user executes a system call?

Q3. In a typical service routine, to go back to the previous code we do RTI. Suppose we replace RTI by a sequence of two instructions:

POPpc

POPpsw

The POPpc instruction will pop the PC value from the control stack (assume that PC, PSW values are on the stack in the right order) and put it into the PC register. The POPpsw instruction will pop the PSW value from the control stack and put it in the PSW register.

Assume that all logical addresses are the same as the physical addresses.

Will this scheme work? Explain in LESS THAN 50 WORDS.

Q 4. Consider the Figure 2.2 (Running Many) in Remzi. Can the program output the following subsequence? Explain.

A

A

A

A

B

A

Q5. In Fig 2.5 (A Multi-threaded), suppose the program was called with argument 1000. What is the MINIMUM possible value of counter printed at the end?