Q1: Consider the below object declarations. signal sig1: std_logic_vector (7 downto 0):="10010101"; signal sig2, sig3, sig4: std_logic_vector; constant c: integer: = 32; C_AMO_TEM_035_02 Page 1 of 11 ASIC Design (ELEC30003.2)-Fall-21-CW2 (Assignment)-QP type OP1 is (LOAD, STORE, ADD, SUB, MUL, DIV); subtype SUB_OP is OP1 range ADD to DIV; signal A: OP1:=store; signal B: SUB_OP; Signal P: integer:=-7; Signal Q: integer:= 4; Signal X, Y: integer range -10 to 10; type VALUE is array (0 to 7) of integer range 0 to 128; constant NUM: VALUE:=( 1, 2, 4, 8, 16, 32, 64, 128); signal RESULT:integer; Determine the output after initial execution of following codes. Justify your answer. Explain if there is any error. a. case A is when load => B RESULT B B