Q1: Designing a flip-flop: A. Construct a JK flip-flop using a D flip-flop, a two-to-one-line multiplexer, and a minimal number of logic gates. The truth table for a JK flip flop is as follows: J K CLK Q(t+A) X Else 20) 0 0 (Rising Edge) Q(1) 0 1 (Rising Edge) 0 1 0 (Rising Edge) 1 1 1 (Rising Edge) Q(t) B. Given the input waveforms below, sketch the output Q for a D flip-flop CLK D