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Q.1) Mark the following statements as true or false and correct the second part if false: 1. The main building blocks of microcomputer are: General

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Q.1) Mark the following statements as true or false and correct the second part if false: 1. The main building blocks of microcomputer are: General registers, operands, ALU, and flags. 2. The elements of Bus Interface Unit are: General registers, operands, ALU, and flags. 3. Assembler is the program that translates object code to equivalent assembly code of 8086. 4. The addressing mode of the MOV AX [BX+SI+0400h]; is a register for the source and based for destination 3. The addressing modes are categorized into many types: integer data type, Binary-Coded Decimal numbers, and, ASCII code. 6. The 16 bit flag of 8086 microprocessor is responsible to indicate the result of subtraction. 7. In the based addressing mode the physical address calculate by form. PA={CS):{DI 8. The instruction. MOV DX, [DIJ+3412H is an example of. Based-Indexed Addressing Mode 9. When the current values of the SS register - 3000h and SP register - FFDOh. The data currently held in the stack are: 64 words. 10. When the content of registers: CS-1234h. IP-0006h. SS-ABCDh and SP-AA00h. The bottom of stack and the end of stack are: AACDOh and AB006h 11. Intel processors CoreTM i3. CoreTM i5, and CoreTM i7 have 16bits. 32bits, and 32bits data bus respectively 12. The double word 3B4C0065h is alimed and represent the segment base address=4C65h and offset=3B00h 13. The memory address space in 8086 is IMbytes for memory and 10 address space. 14. For the development of assembly language program, the syntax error tested by using the assembler and the logical error testing by using the debug. 15. The double word 66BBCC55 stored in memory location 123CCh is aligned. (45 Marks) Q.2) A) Encode the following instructions using the tables in appendix: 1. MOV DS, DX 3. SUB (BP+DI+FE$6h) 8E7CH 2. MOV (BP+DI+CDEFN), 56h 4. AND [BP+SI+34h). ABCDH (40 Marks) B) Name the internal registers of 8086. Table the combination of registers to form the physical addresses for memory segments

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