Q2 (25Marks) For the following VHDL code: 1. Draw the internal design of the circuit (RTL). 2. Draw the z output waveform in relation to the clock if x=(10), and y=(5), 3- What specific function does this circuit perform? library TREES use IEEL. 5TD_10620_1104. ALD; use IEEE.STD LOGIC UNSIGNED.ALL: entity examin Port ( cik : in std_logie; sol : in STD LOGIC VECTOR (1 downto 0); x,y: in SID_LOGIC_VECTOR (7 downto 0); z : out STD_3051C_VECTOR (7 downto 0)); end exam architecture Behavioral of exam is begin process (olk, sol,x,y) variable teep: atd_logic_vector (7 downto 0); begin CASE el 18