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Q2. (50%) For the multiply-and-accumulate circuit shown below ancdf 16 The design performs computation acc-a b+acc/2 Please use behavioral modeling (similar to HW2) to describe

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Q2. (50%) For the multiply-and-accumulate circuit shown below ancdf 16 The design performs computation acc-a b+acc/2 Please use behavioral modeling (similar to HW2) to describe all three registers (positive edge triggered, active high synchronous reset); and data flow modeling to describe the combination logic for a*b+acc/2 Then use the structure modeling to combine them together Use the following module template to complete the design module multiply and accumulate(acc,a,b.clk,rst input [7:01 a,b // two 8-bit input input clk; ands is 20 time units l clock // active high output 16:01 acc / 17-bit ou * declare local variables ra, rb and c here * describe 3 registers with behavioral modeling here * describe multiplier and adder with data flow modeling here endmodule Note: you can use either two assign" statements for multiplier and adder respectively or just one "assign" statement to describe them both in the same expression Note: besides the multiply and accumulate module, you should write a stimulus module to test your design. The input waveforms shown below time 0 020304 0 clk rst a 7:0] 3 25 63 127 3 b7:01 4 75 21 4 Q2. (50%) For the multiply-and-accumulate circuit shown below ancdf 16 The design performs computation acc-a b+acc/2 Please use behavioral modeling (similar to HW2) to describe all three registers (positive edge triggered, active high synchronous reset); and data flow modeling to describe the combination logic for a*b+acc/2 Then use the structure modeling to combine them together Use the following module template to complete the design module multiply and accumulate(acc,a,b.clk,rst input [7:01 a,b // two 8-bit input input clk; ands is 20 time units l clock // active high output 16:01 acc / 17-bit ou * declare local variables ra, rb and c here * describe 3 registers with behavioral modeling here * describe multiplier and adder with data flow modeling here endmodule Note: you can use either two assign" statements for multiplier and adder respectively or just one "assign" statement to describe them both in the same expression Note: besides the multiply and accumulate module, you should write a stimulus module to test your design. The input waveforms shown below time 0 020304 0 clk rst a 7:0] 3 25 63 127 3 b7:01 4 75 21 4

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