Q2 (a) The schematic diagram of a flip-flop is as shown in Figure 2.1. S Q > C R Figure 2.1 A schematic digram of a flip-flop It is known that, before interval 1, the output states are Q = 1 and Q = 0. Sketch the output states Q and Q, given that the S, R and C signals are as in Figure 2.2. [Leave bank and write i for indeterminate condition] S od 3 3 9 10 11 Figure 2.2 Timing diagram for flip-flop (10 marks) i. Explain what occured to signal Q in the intervals 1, 2 and 3. (7 marks)