Q2) Design (draw) a circuit that receives the following control inputs and data inputs to produce the following outputs. You will need 4 flip-flops connected to make a 4 bit register named W[3:0). 4 bit register inputs are WD[3:0), and its output Q pins are WQ[3:0). Input Clk is a clock signal that comes as clock pulses. R is the asynchronous reset for W. R= 1 makes WQ=0000; R=0 allows data to be clocked in to W. Input A[3:0) is a 4 bit wide data bus. Input IR[1:0] is 2 bits wide and acts as control signals. When IR bits = 00, a clock pulse directly loads A[3:0) into W[3:0] (values appear at WQ). When IR bits = 01, a clock pulse loads -WQ[3:0) into W[3:0] (values appear at WQ). When IR bits = 10, a clock pulse shifts W[3:0] right one bit position. W[3] gets 0. When IR bits = 11, a clock pulse rotates W[3:0) right one bit position. W[3:0]