Question: For the following we consider instruction encoding for instruction set Architectures. a) Consider the case of a processor with an instruction length of 12 bits

For the following we consider instruction encoding for instruction set Architectures.

a) Consider the case of a processor with an instruction length of 12 bits and with 32 general purpose registers so the size of the address fields is 5 bits. Is it possible to have instruction encoding for the following: 

3 two- address instructions

30 one address instructions

45 zero address instructions

b) Assuming the same instruction length and address field sizes as above, determine if it is possible to have 

3 two- address instructions

31 one address instructions

35 zero address instructions

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