Q3) 5-stages processor has the following latencies: Hint: latency= execution time of 1 instruction a) If the processor is a single cycle non-pipelined what is the cycle time for the processor? What is the latency of an instruction for the processor? b) If the processor is pipelined what is the cycle time for the processor? What is the latency of an instruction for the processor? c) (Extra Credits) If you could split one of the pipeline stages into 2 equal halves, resulting into 6 stages which one would you choose? What is the new cycle time? What is the new latency