The 5 stages of the processor have the following latencies: a. b. Fetch 300ns 200ns Decode 400ns 150ns Execute 350ns 100ns Memory Writeback 550ns 100ns 190ns 140ns Assume that when pipelining, each pipeline stage costs 20ns extra for the registers between pipeline stages. I. Non-pipelined processor: what is the cycle time? What is the latency of an instruction? What is the throughput? II. What is the cycle time? What is the latency of an instruction? What is the throughput? III. If you could split one of the pipeline stages into 2 equal halves, which one would you choose? What is the new cycle time? What is the new latency? What is the new throughput?