Q3. In the single cycle CPU the following are the latencies for different components: I-Mem Add Mux ALU Regs D-Mem SienExtend Shiftleft2 500 pS150 ps 100 ps 180 ps 220 ps 1000 ps 90 ps 20 ps Assume all other components have zero latency. Only R-format instructions need to be executed. Do stagewise anaylsis () What are the stages that need to be executed? (i) What is the critical path for each stage and what is the critical path latency for each? (ii) What is the maximum possible frequency of the CPU clock given the latencies