Q3. In the single cycle CPU the following are the latencies for different components: ALU Regs D-MemSignExtend Shiftleft2 -Mem Add Mux 20 pS 500 ps150 ps100 ps180 ps220 ps1000 ps 90 ps Assume all other components have zero latency. Only R-format instructions need to be executed. Do stagewise anaylsis (i) What are the stages that need to be executed? (ii) What is the critical path for each stage and what is the critical path latency for each? (ii) What is the maximum possible frequency of the CPU clock given the latencies