Q4) Consider the following sequence of instructions, and assume that it is executed on a 5 -stage pipelined data path (IF, D/R, ALU, DM, WB, Also assume that writing into a register happens in the first. half of the clock cvcle whit.. ing from a register happens in the second half of the clock cycle: List the read-after-write data dependencies. As an example, x on y(St5) shows instruction x has data dependency on instruction y since it is reading register $+5