Q5) A combinational circuit with internal signals and signal propagation delays

Shown below is a combination circuit that takes 5 inputs (L0, L1, L2, L3, and Comp), and generates 4 outputs (L4, L5, L6, L7).

Please design the entity as well as the test bench for this combinational circuit. In your design, please set up internal signals A1, B1, A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7 and B7.

Your entity design is:

Your test bench design is:

In your test bench design, please let L0, L1, L2, L3 to go through 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111, each at a period of 100ns. Do this for COMP = 0 first, and then let COMP = 1.

The result waveforms (COMPS = 0) are:

Please select the signals to be simulated in the following order: L0, L1, L2, L3, COMP, L4, L5, L6, L7.

The result waveforms (COMPS = 1) are:

Please add a propagation delay of 4ns for the OR gate, and 10ns for the XOR gate in your entity design. In this case, your entity design is:

Using the same test bench, result waveforms (COMPS = 0) are:

Please pay attention to the propagation delay in your simulation results.

The result waveforms (COMPS = 1) are: