Q6: A JK flip flop is used to realize a Toggle (T) flip flop by tying both inputs together to a single value as shown. When T-1, the output will toggle, and when T 0, it will hold. At time t 0, T- Clk 0. One clock period is 2ns. At time t 3ns, T- 1. Draw a timing diagram showing the output Q from t = 0 to 8ns. Assume Q 0 at time t-0. (15) SET CLR