Ques $8$: I have a pipelined design with $10$ stages. Consider that a set of $100$ sequential instructions are executed on this hardware and $20\%$ of these instructions result in errors. All instruction errors are detected in the third stage, triggering pipeline flush. If the pipeline is in steady$-$state before executing these sequential instructions, what is the average CPI obtained for these instructions. You can assume that the error dissapear upon re$-$execution.