Question 1. A new addressing mode
Question 1. A new addressing mode Consider adding a new addressing mode to the variation 4 MIPS. The addressing mode adds two registers get the effective address for accessing the memory for loads and stores. We would like to implement this new addressing mode while changing the MIPS hardware as little as possible. Our compiler will be changed so that code sequences of the form: are changed to: LWI R4, (R1+R2) DADD R3, R1, R2 LW R4, #0 (R3) DADD R3, R1, R2 SWI (R1+R2), R4 SW #0 (R3), R4 a) What fields are required for the new instructions? For the LWI and SWI, show the required fields, and explain the function of each field. Do you think the new instructions should be i-type, r-type, or 1-type? Try to map what you need to existing fields in a way that you can use parts of the existing data paths as much as you can. b) Describe the work that would need to be done in each of the five pipeline stages when running a LWI instruction. Repeat, but for a SWI instruction. c) Modify the diagram of the variation 4 MIPS hardware posted on Springboard to show the changes to the hardware that would be needed to accommodate the LWI and SWI instructions. Describe the changes at a high level. Be sure to explain why you are making each change. d) Suppose that in your original MIPS code 35% of all instructions are loads and stores. Also, suppose that this new addressing mode can be used for 8% of the load and stores, in other words, 8% of the original loads and stores follow the pattern in the chart in given, so that two instructions can be replaced with a single instruction. If the original code has an instruction count of 1000 instructions, what is the instruction count for the code on the enhanced MIPS? e) Which machine runs the code faster? (Calculate speed-up, and interpret the result. Assume both machines use the same clock cycle time.) Question 1. A new addressing mode Consider adding a new addressing mode to the variation 4 MIPS. The addressing mode adds two registers get the effective address for accessing the memory for loads and stores. We would like to implement this new addressing mode while changing the MIPS hardware as little as possible. Our compiler will be changed so that code sequences of the form: are changed to: LWI R4, (R1+R2) DADD R3, R1, R2 LW R4, #0 (R3) DADD R3, R1, R2 SWI (R1+R2), R4 SW #0 (R3), R4 a) What fields are required for the new instructions? For the LWI and SWI, show the required fields, and explain the function of each field. Do you think the new instructions should be i-type, r-type, or 1-type? Try to map what you need to existing fields in a way that you can use parts of the existing data paths as much as you can. b) Describe the work that would need to be done in each of the five pipeline stages when running a LWI instruction. Repeat, but for a SWI instruction. c) Modify the diagram of the variation 4 MIPS hardware posted on Springboard to show the changes to the hardware that would be needed to accommodate the LWI and SWI instructions. Describe the changes at a high level. Be sure to explain why you are making each change. d) Suppose that in your original MIPS code 35% of all instructions are loads and stores. Also, suppose that this new addressing mode can be used for 8% of the load and stores, in other words, 8% of the original loads and stores follow the pattern in the chart in given, so that two instructions can be replaced with a single instruction. If the original code has an instruction count of 1000 instructions, what is the instruction count for the code on the enhanced MIPS? e) Which machine runs the code faster? (Calculate speed-up, and interpret the result. Assume both machines use the same clock cycle time.)
