Question #1

A single instruction is to execute on both a single cycle processor with a clock cycle time of 800ps and on a 5-stage pipelined processor with a clock cycle time of 200ps. There are no delays. What is true about this comparison?

	A.	The single cycle processor will complete the instruction 200ps before the pipelined.
	B.	The pipelined processor will complete the instruction 600ps before the single cycle.
	C.	The pipelined processor will complete the instruction 200ps before the single cycle.
		Question #2 Consider the following code. If the write register value is not copied through the pipeline for the add instruction, what register will the add write to in the WB stage? add $s1, $s2, $s3 sub $t4, $t5, $t6 addi $s3, $s5, 5 sub $t1, $t2, $t3 a. $s3 b. $t4 c. $s1 d. $t1 Please show the work for both questions so I can understand how they are done. Thank You