QUESTION 2 (12 marks) Design a general-purpose processor that implements the following instruction set: MOVMR direct, Rm; % M[direct] = Rm SUBRMR Rn, direct, Rm; % Rn = M[direct] - Rm; ADDMMR direct1, direct2, Rn; % M[direct1] = M[direct2] + Rn a. Define instruction fields and their sizes, IR aliases, and registers and memory size declarations. (3 points) b. Design the processor's datapath. Specify the size of each connection/port. (5 points) C. Design the controller FSM. (4 points) Only design the processor for the instruction set given above. Do NOT include any functional units and/or connections that are not related to the execution of the above given instructions. 5 Given below is the sample datapath developed in class for a different instruction set. Obviously, your datapath for this exam question should be different from the one given below but you can use the datapath below as a guide in designing the datapath for the above given instruction set. Control unit Datapath RFS To all input control signals 2x1 mux RFwa RFw Controller (Next-state and control logic; state register) RFwe From all output RF (n) RFria RFrie Given below is the sample datapath developed in class for a different instruction set. Obviously, your datapath for this exam question should be different from the one given below but you can use the datapath below as a guide in designing the datapath for the above given instruction set. Control unit Datapath RES To all input control signals 2x 1 mux RFwa RFw Controller (Next-state and control logic state register) RFwe RF (n) From all output control signals RFrla RFrie n RFr2a Peld Irld PC RFr! RFr2 IR PCinc RFr2e ALUS PCele ALU ALUZ 2 Ms 3xl mux Mre Mwe A Memory D QUESTION 2 (12 marks) Design a general-purpose processor that implements the following instruction set: MOVMR direct, Rm; % M[direct] = Rm SUBRMR Rn, direct, Rm; % Rn = M[direct] - Rm; ADDMMR direct1, direct2, Rn; % M[direct1] = M[direct2] + Rn a. Define instruction fields and their sizes, IR aliases, and registers and memory size declarations. (3 points) b. Design the processor's datapath. Specify the size of each connection/port. (5 points) C. Design the controller FSM. (4 points) Only design the processor for the instruction set given above. Do NOT include any functional units and/or connections that are not related to the execution of the above given instructions. 5 Given below is the sample datapath developed in class for a different instruction set. Obviously, your datapath for this exam question should be different from the one given below but you can use the datapath below as a guide in designing the datapath for the above given instruction set. Control unit Datapath RFS To all input control signals 2x1 mux RFwa RFw Controller (Next-state and control logic; state register) RFwe From all output RF (n) RFria RFrie Given below is the sample datapath developed in class for a different instruction set. Obviously, your datapath for this exam question should be different from the one given below but you can use the datapath below as a guide in designing the datapath for the above given instruction set. Control unit Datapath RES To all input control signals 2x 1 mux RFwa RFw Controller (Next-state and control logic state register) RFwe RF (n) From all output control signals RFrla RFrie n RFr2a Peld Irld PC RFr! RFr2 IR PCinc RFr2e ALUS PCele ALU ALUZ 2 Ms 3xl mux Mre Mwe A Memory D
