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Question 2 9 A 4 - bit load register has input d 0 d 1 d 2 d 3 and output q 0 q 1
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A bit load register has input dddd and output Which of the following is true when the clock input and r both high?
The register's bits are set to
The register's bits are set to
The register maintains the previously loaded value
The register loads a new input value
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