Question 2. Comparing the four instruction set architectures Please base your answers on the code in the posted solutions (rather than on the code you turned in). Make a table to compare the four architectures, showing: (a) The code size in bytes needed to implement A= A*B+C+D. [Note which architectures result in less demand for program memory.] (b) The percentage efficiency of the code. This is the percentage of code bits that are useful, that is, not just zero-filled to make all instructions a fixed length. [Note which architectures use program memory more efficiently.] (c) The number of bytes of data transferred between the data memory and the processor when running the code. [Note which architectures require fewer data transfers.] (d) The total number of bytes (both data and program) transferred to/from memory in the course of running the code. [This is a very important metric for self-powered applications, since accessing memory is one of the most power-hungry things a processor does. Note which architectures will consume less power consumption due to memory transfers.] (e) The CPU time for each architecture (from Module 1 HW solutions). It's worth thinking about the trade-offs this table shows in terms of the advantages of various architectures (for this admittedly simplistic example code). Question 2. Comparing the four instruction set architectures Please base your answers on the code in the posted solutions (rather than on the code you turned in). Make a table to compare the four architectures, showing: (a) The code size in bytes needed to implement A= A*B+C+D. [Note which architectures result in less demand for program memory.] (b) The percentage efficiency of the code. This is the percentage of code bits that are useful, that is, not just zero-filled to make all instructions a fixed length. [Note which architectures use program memory more efficiently.] (c) The number of bytes of data transferred between the data memory and the processor when running the code. [Note which architectures require fewer data transfers.] (d) The total number of bytes (both data and program) transferred to/from memory in the course of running the code. [This is a very important metric for self-powered applications, since accessing memory is one of the most power-hungry things a processor does. Note which architectures will consume less power consumption due to memory transfers.] (e) The CPU time for each architecture (from Module 1 HW solutions). It's worth thinking about the trade-offs this table shows in terms of the advantages of various architectures (for this admittedly simplistic example code)
