Question 2 Digital Systems A designer wanted to synthesise combinational logic represented by the truth table in Table 1 , where a,b,y are single-bit logic signals and the symbol X represents 'don't care'. TABLE 1: The truth table for Question 2. To represent the behaviour specified by the truth table, the designer wrote the following SystemVerilog code: always_comb if (a!=b) if (a) y=1b0 else y=1b1 The above description simulated correctly, but the synthesis tool failed to infer correct hardware. Explain why the synthesis failed and suggest a SystemVerilog implementation that would synthesise correctly