Question 2. VHDL design (5 points) 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 entity ExamKernel is Port ( cik : in std_ulogic; rst : in std_ulogic; X : in integer_array(0 to 3); Y : in integer_array(0 to 3); z : in integer_array(0 to 3); output : out integer ); end ExamKernel; architecture Behavioral of ExamKernel is begin calculate: process (clk, rst) is variable sum: integer; begin if (rst = '1') then output