QUESTION 2 What instruction will require more than a single clock-cycle to be executed? None STR R1, [R2, LSL #31 SUB R10, R9, R8, LSR #4 RSBGT R0, R0, #2 LDR R1 , [R3,#41 EORS R1, R3, R0 AND RO, R1, R2 BEQ Stop MOV R11, R3, ROR #2 ADDEQ RI, R12, R0, LSL #3