Question $3.$ Consider individual stages of the datapath that have the following latencies:

a$.[5$ points$]$ What is the clock cycle time in a pipelined and a non$-$pipelined processor?

b$.$ Suppose the MEM stage is split into three separate stages, each with a latency of $1ns.$

i$.[5$ points$]$ How many stages will the new processor have?

ii$.[5$ points$]$ What is the new clock cycle time in a pipelined and a non$-$pipelined processor?