Answered step by step
Verified Expert Solution
Link Copied!

Question

1 Approved Answer

Question 3: Here you are asked to show how one particular sequence of memory references would perform (in terms of hit and miss) on a

image text in transcribed

Question 3: Here you are asked to show how one particular sequence of memory references would perform (in terms of hit and miss) on a 2-way sct associative cache. The ize of cache is 4 blocks and the cache block size is 4-byte The memory is addressed by byte. Suppose the following sequence of memory references arrive at cache in order Cache size block u byte Reference #1> Address: 000000110 Reference #2> Address: 000000100 t set no Reference #3> Address: 001000010 Block Srze Reference #42 Address: 000001000 Reference #52 Address: 01 1001000 Specify if the memory references are a cache miss or hit. Then use the tables below to show the state of the cache just after every memory reference completes. 2-Way Set Associative: initial state Set (1-bit) Valid Tag (6bit) Data (1-byte 2-way Set-Associative-after reference #1 Set (1-bit) Valid Tag (6bit) Data (4-byte 2-way Set-Associative: after reference #2 Set (1-bit) Valid Tag (6-bit) Data (4-byte) 2-way Set-Associative: after reference #3 Set (1-bit Valid Tag (6-bit) Data (4-byte 2-Way Set-Associative after reference #4 Set (1-bit) Valid Tag (6-bit) Data (4-byte) 2-Way Set-Associative, after reference #5 Set (1-bit) Valid Tag (6-bit) Data (4-byte Page 2 of 3 An Question 3: Here you are asked to show how one particular sequence of memory references would perform (in terms of hit and miss) on a 2-way sct associative cache. The ize of cache is 4 blocks and the cache block size is 4-byte The memory is addressed by byte. Suppose the following sequence of memory references arrive at cache in order Cache size block u byte Reference #1> Address: 000000110 Reference #2> Address: 000000100 t set no Reference #3> Address: 001000010 Block Srze Reference #42 Address: 000001000 Reference #52 Address: 01 1001000 Specify if the memory references are a cache miss or hit. Then use the tables below to show the state of the cache just after every memory reference completes. 2-Way Set Associative: initial state Set (1-bit) Valid Tag (6bit) Data (1-byte 2-way Set-Associative-after reference #1 Set (1-bit) Valid Tag (6bit) Data (4-byte 2-way Set-Associative: after reference #2 Set (1-bit) Valid Tag (6-bit) Data (4-byte) 2-way Set-Associative: after reference #3 Set (1-bit Valid Tag (6-bit) Data (4-byte 2-Way Set-Associative after reference #4 Set (1-bit) Valid Tag (6-bit) Data (4-byte) 2-Way Set-Associative, after reference #5 Set (1-bit) Valid Tag (6-bit) Data (4-byte Page 2 of 3 An

Step by Step Solution

There are 3 Steps involved in it

Step: 1

blur-text-image

Get Instant Access to Expert-Tailored Solutions

See step-by-step solutions with expert insights and AI powered tools for academic success

Step: 2

blur-text-image

Step: 3

blur-text-image

Ace Your Homework with AI

Get the answers you need in no time with our AI-driven, step-by-step assistance

Get Started

Recommended Textbook for

Machine Learning And Knowledge Discovery In Databases European Conference Ecml Pkdd 2015 Porto Portugal September 7 11 2015 Proceedings Part 1 Lnai 9284

Authors: Annalisa Appice ,Pedro Pereira Rodrigues ,Vitor Santos Costa ,Carlos Soares ,Joao Gama ,Alipio Jorge

1st Edition

3319235273, 978-3319235271

More Books

Students also viewed these Databases questions

Question

Describe the five elements of the listening process.

Answered: 1 week ago