QUESTION 3 Which one of the following VHDL Process() statements could be used as part of a 100 Mhz to 10 Hertz clock scaler, where the 10 Hertz signal is syncronized to the negative going edge of the 100 Mhz clock? Assume that the Clk_100_Mhz H input clock signal and Clk_10_Hz H output signal, are already declared in the Port statement for the Scaler model. Note this question is worth 10 points. O a. signal Counter_100_Hz. integer = 0; Process (Clk_100_Mhz_H) is Begin if (Clk_100_Mhz'event AND Cik_100_Mhz = '0') then -- after the clock edge the signal should be zero Counter_100_Hz