Question 30 (4 points) d D Q CLK> Suppose that the in the circuit above the propagation delay of the inverter is 2.5 ns and the propagation delay and settup times of the flip-flop are 2.5 ns and 3 ns respectively. What is the shortest clock period for the circuit that will not violate the time constraints? 3.5 ns 5.5 ns 8 ns None of the above