Question 4 ( 15 Points) symmetric shared-mesed multiprocessor illustrated in the following figure represents commonly implemented with four blocks eoherence protocol discussed in class, and shown in the figure. Each cache is direct-mapped address and cach word shows only twords. To simplify the illustration. the cache address tag contains the full states are denoted M,S, and a for Modified. Shared. and invalid. For each part assume the initial cache and memory state as illustrated in the figure. Each part ol this exercise specifies a sequence of one or more CPU operations of the form: P\#:

[] Where P\# designates the CPU (e.g., PO), > is the CPU operation (e.g., read or write), > denotes the memory address, and > indicates the new word to be assigned on a write operation. Treat each part below as independently applied to the initial state as given in figure. What is the resulting state (i.e., coherence state, tags, and data) of the caches and memory after the given action? Show only the blocks that change, for example, P0.B0: (I,120,00 01) indicates that CPU P0's block BO has the final state of 1 , lag of 120 , and data words 00 and 01 . Also, what value is returned by each read operation? a) (5 points) P15: read 110 b) (5 points) P0 : write 128

[] Where P\# designates the CPU (e.g., PO), > is the CPU operation (e.g., read or write), > denotes the memory address, and > indicates the new word to be assigned on a write operation. Treat each part below as independently applied to the initial state as given in figure. What is the resulting state (i.e., coherence state, tags, and data) of the caches and memory after the given action? Show only the blocks that change, for example, P0.B0: (I,120,00 01) indicates that CPU P0's block BO has the final state of 1 , lag of 120 , and data words 00 and 01 . Also, what value is returned by each read operation? a) (5 points) P15: read 110 b) (5 points) P0 : write 128