Question 4: Assume that the base CPI for a pipelined Datapath on a single core system is 1. - Note that this does NOT include the overhead associated with cache misses!!! Profiles of a benchmark suite that was run on this single core chip with an L1 cache suggest that for every 10,000,000 accesses to the cache, there are 308,752 L1 cache misses. - If data is found in the cache, it can be accessed in 1 clock cycle, and there are no pipe stalls - If data is not found in the cache, it can be accessed in 10 clock cycles Now, consider a multi-core chip system where each core has an equivalent L1 cache: - All cores references a common, centralized, shared memory - Potential conflicts to shared data are resolved by snooping and an MSI coherency protocol Benchmark profiling obtained by running the same benchmark suite on the multi-core system suggests that, on average, there are now 452,977 misses per 10,000,000 accesses. - If data is found in a cache, it can still be accessed in 1 clock cycle - On average, 14 cycles are now required to satisfy an L1 cache miss What must the CPI of the multi-core system be for it to be worthwhile to abandon the single core approach?