Question $5)$ Assume a processor has a fully associative data TLB with $512$ entries, and each b$)$ Now we transpose array b so the code is modified to:

$c[i][j]=c[i][j]+a[i][k]**b[j][k]$;

Fill the following access pattern table with the same assumptions as a$).$ Questions $4)$ Consider the following code performing matrix multiplication.

Assumptions:

The cache is initially empty and caches only array variables.

Size of int: one word $(4$ bytes$)$

Access pattern of data elements is from right to left of the code.

$($access b$,$ a$,$ and then c$)$

a$)$ Assuming a $64$B fully associative cache with block size $16B=4$ words and LRU

replacement policy, fill in the following access pattern table appropriately.

entry can map a $4KB$ page. After a TLB miss, a hardware engine walks the page table to

reload the TLB$.$ The TLB uses a first$-$in$/$first$-$out $($FIFO$)$ replacement policy.

We will evaluate the execution of the following program which adds the elements from three

$2MB$ arrays and stores the results in a fourth $2MB$ array. $($note that, $1MB=1,048,576$ Bytes,

the starting address of the arrays are given below$)$:

Assume that the above program is the only process in the system and ignore any instruction

memory or operating system overheads. The data TLB is initially empty.

What are the total TLB misses for this configuration?