Question 5

Conceptual Foundation System Equation: H/WS/w People Procedures Block Diagram for hardware (H/W) A "conceptual" representation of system hardware. Be prepared to draw CPU component down to "register" level detail Software Architecture Diagram for software (S/w) Computer Hardware Inside the CPU 1: ALU - What is purpose of? Registers General (Areg, Breg, Base, Index) Q2: What are INTEL equivalents of conceptual general registers? VS Special Purposed MARMemory Address register MDRMemory Data register IR - Instruction register IP- Instruction Pointer register BUSinternal vs external busing CPU Cycling FETCH Decode -> Execute Cycling Q3: What happens during EACH cpu cycle? Compute cycle time (ct) of CPU c (t) 1/CPU speed expressed in nano or pico seconds Q4: What is cycle time of 3Ghz CPU? 5: How much time (ns, ps) is required to complete hilevel: result(a-b) / (c+d) Q6: What are the steps of instruction fetch cycle? Fetch TO Fetch * T1 MAR- IP Control: read memory IR Execute Cycling Q3: What happens during EACH cpu cycle? Compute cycle time (ct) of CPU c (t) 1/CPU speed expressed in nano or pico seconds Q4: What is cycle time of 3Ghz CPU? 5: How much time (ns, ps) is required to complete hilevel: result(a-b) / (c+d) Q6: What are the steps of instruction fetch cycle? Fetch TO Fetch * T1 MAR- IP Control: read memory IR