Question 5 Not yet answered Marked out of 10.00 Flag question Find the time delay for the delay subroutine shown below if the system has a PIC18 with a frequency of 16MHz: a MOVLW D'200' MOVWF 0x40 BACK MOVLW D'100' MOVWF OX41 LOOP NOP NOP DECF 0x41, F BNZ LOOP DECF 0x41, F BNZ LOOP DECF 0x40, F BNZ BACK TABLE 20-2: PIC18FXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles Status Affected Notes MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f. d, a Add WREG and ADDWFC f. d, a Add WREG and Carry bit of ANDWF f. d, a AND WREG with CLRF 1, a Cleart COMF 1. d, a Complement CPFSEQ f, a Compare f with WREG skip = CPFSGT f, a Compare f with WREG skip > CPFSLT f, a Compare with WREG skip DECF I, d, a Decrement DECFSZ f. d, a Desrement, Skip to DCFSNZ f.d, a Decrement . Skip it Noto INCF 1, d. a Increment INCEST 1 0010 oldad 1 0010 Oda 1 0001 01 da 1 0110 101a 1 0001 12 da 1 (2 or 3) 0110 1 001a 1 (2 or 3) 0110 010a 1 (2 or 3) 0110 000a 1 0000 olda 1 (2 or 3) 0010 11 da 1 (2 or 3) 0100 11da 1 0010 10da TEE tret EEEE ffff PECE EEEE EEEE EEEE EEEE EEEE EEEE FEEE EEEE C, DC, Z. OV, N 1,2 fett C, DC, Z, OV, N 1,2 IEEE IZN 1.2 fEEE Z 2 fett ZN 1,2 EEEE None 4 EEEE None 4 None 1,2 fEEt C, DC, Z. OV, N 1, 2, 3, 4 EEEE None 1, 2, 3, 4 IEEE None 1,2 EEEE C, DC, Z, OV, N 1, 2, 3, 4 TABLE 20-2: PIC18FXXX INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Operands Description Cycles Status Affected Notes MSb LSD EEEE ta EEEE EEEE ter EEEE EEEE tet EEEE EEEE BYTE-ORIENTED FILE REGISTER OPERATIONS ADOWF 1.d, a Add WREG and ADDWFC da Add WREG and Carry bit to ANDWF 1.d, a AND WREG with CLRF ta Cleart COMF 1. da Complement ! CPFSEO ta Compare with WREG, skip CPFSGT Compare with WREG skip > CPFSLT La Compare with WREG. Skip DECF 1d, a Decrement DECFSZ td, a Decrementi, Skip to DCFSNZ 1.d, a Decrement Skip Not O INCF td, a Increment INCFSZ 1.d. a Increment Skip to INFSNZ 1.d, a increment Skip if Not IORWF 1.d. a Inclusive OR WREG with MOVF td, a Movet MOVFF 14 Move t, (source) to 1st word (destination) and word MOVWF La Move WREG 101 MULWF f.a Multiply WREG with NEGF La Negatet RLCF Id, a Rotate Left through Carry RLNCF 1.d, a Rotate Left (No Carry) RRCF 1.d, a Rotate Right through Carry RRNCF td, a Rotate Right 1 (No Carry) SETF La Sett SUBFWB f.d, a Subtract from WREG with borrow SUBWF 1.d, a Subtract WREG from SUBWFB 1.d. a Subtract WREG from with borrow SWAPF f.d, a Swap nibbles in TSTFSZ fa Testf, skipio XORWF td, a Exclusive OR WREG with BIT-ORIENTED FILE REGISTER OPERATIONS BCF 1.b, a Bit Clear BSF b, a Bi Sett 1 2010 Olda 1 0010 Oda 1 0001 01da 1 0110 1010 0001 12da 1 (2 or 3) 0110 001a 1 (2 or 3) 0110 010a 1 (2 or 3) 0110 000 1 0000 oida 1 (2 or 3) 0010 11da 1 (2 or 3) 0100 12 da 1 0010 10da 1 (2 or 3) 0011 11da 1 (2 or 3) 0100 10da 1 0001 ooda 1 0101 odda 12 2100 EEEE 1111ttes 0110 111a 0000 001 0110 1100 0011 olda 0100 olda 0011 ooda 0100 ooda 0110 100 0101 oida IEEE TERE ter EEEE EEE tret EEEE EEEE LEEE tett frit fire EEEE EEE fer EEEE EEEE C, DC, Z, OV, N 1,2 free C, DC, Z, OV, N 1.2 tett ZN 1,2 EEEE Z fier IZN 1,2 EEEE None EEEE None IEEE None 1,2 IEEE C, DC, Z, OV, N 1, 2, 3, 4 EEEE None 1.2.3.4 rrer None 1.2 IEEE C, DC, Z. OVN 1, 2, 3, 4 FREE None Pre None 1,2 FEEE Z.N 1,2 fit ZN tret None tett IEEE None EEEE None IEEE C. DC, Z. OVN 1.2 Ett C.ZN tret ZN 1.2 EEE C. ZN trt ZN cert None EEEE C. DC, Z, OV, N 1,2 1 1 0101 0101 12da 10da ret EEEE Ett C, DC, Z, OV, N IEEE C, DC, Z, OV, N 1,2 1 0011 1 (2 or 3) 0110 0001 10da 011 10da TELE fett None TECE None FEE (ZN 1.2 fit 1001 bbba 1000 bbba TEET EFET fret None Et None 1,2 1,2 ON XORWF 1. d, a Exclusive OR WREG with f 0001 10da TELE EEE ZN BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b, a Bit Cleart 1 1001 bbba feet fitt None 1.2 BSF 1.b. Bit Seti 1 1000 bbba EEEE fEEt None 1,2 BTFSC 1, b, Bit Testi, Skip it Clear 1 (2 or 3) 1011 bbba EEEE ferr None 3,4 BTFSS 1. b, a Bit Test 1, Skip it Set 1 (2 or 3) 1010 bbba EEEE fref None 3,4 BTG 1. d, a Bit Toggle + 1 0111 bbba fEEt None 1,2 Note 1: When a PORT register is modified as a function of itself (e.g.MOVE PORTB, 1.0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0. 2: If this instruction is executed on the TMRO register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a Nor, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction 5: the Table Write starts the write cycle to internal memory, the write will continue until terminated. TABLE 20-2: PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Status Affected Notes Description Cycles Mnemonic, Operands MSb LSb CONTROL OPERATIONS BC n Branch i Carry BN n Branch if Negative BNC n Branch If Not Carry BNN n Branch it Not Negative BNOV n Branch Not Overflow BNZ Branch if Not Zero n Branch it Overflow BRA n Branch Unconditionally BZ n Branch Zero CALL ns Call subroutine1st word 2nd word 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0010 0110 0013 0111 0101 0001 0100 Onnn 0000 1100 kkkk 0000 - nnnn nnnn None in None nnnn nnnn None nnnn None nnnn nnnn None nnnn ninn None nnnn None nnnn nnnn None nnnn nnnn None kkkk kkkk None kkkk 0000 0100 TO, PB 00 0111 C n BOV kkkk Thu CALL ns NO CLRWDT DAW GOTO Ils III Call subroutineist word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device RESET Return from interrupt enable 110s kkkk 0000 0000 1111 kkkk 0000 XXXC 0000 0000 NOP NOP POP PUSH RCALL RESET RETFIE 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1112 0001 nnnn None kkkk None kkkk 0100 TO, PD 0111 C kkkk None kkkk 0000 None XXXX None 0710 None 0101 None nnnn None 1111 IANI 0003 GIE/GIEH PEIE/GIEL kkkk None 0013 None 0011 TO, PD n 1 5 0000 0000 RETLW RETURN SLEEP k 5 Return with literal in WREG Return from Subroutine Go into Standby mode NN 0000 0000 0000 1100 0000 0000 kkkk 0001 0000 TABLE 20-2: PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles Status Affected Notes MSb LSD LITERAL OPERATIONS ADDLW k Add literal and WREG ANDLW k AND literal with WREG IORLW K Inclusive OR literal with WREG LFSR 1.k Move literal (12-bit) 2nd word to FSRx 1st word MOVLB K Move literal to BSR 1 1 1 2 0000 0000 0000 1110 1111 0000 1111 1011 1001 1110 0000 0001 kkkk kkkk kkkk 0001 kkkk 0000 kkkk kkkk kkkk kkkk kkkk kick C. DC, Z, OV, N IZN ZN None None SLEEP Go into Standby mode 00000000 00000000 0001 0000 00 None 0012 TOP5 TABLE 20-2: PIC18FXXX INSTRUCTION SET (CONTINUED) Mnemonie, Operando Description Cycles 16-Bit Instruction Word MSD LSD Statu Affected Notes kkk C, OG ZON ZN KZN N None LITERAL OPERATIONS ADOLW Adderal and WREO ANDLW AND Mal with WREG ORLW Inclusive Oral with WREG 1 UFSR Move Meral (12-2nd word to FSR word MOV Move Berat BSR 30 1 MOVLW Move Healto WREO 10 MULLW Multiply Iteral with WREG 11 RETLW Platum within WREG 2 SUBLW Subtract WREG from Heral 11 XORLW Exclusive OR er with WREG DATA MEMORY PROGRAM MEMORY OPERATIONS TERD Table Read TBLRD - Table Read with post increment TOLADA Read with postremo TBLRO." Tobleed with pre-creen TALWT Table Wire 2 TILLWT. Table Wie with postin TELWT Table Witte with pool crement TELWT. 09061111 0000 101 kkkk 1000 1001 11101110 DEE 1111 0000 00000000000 00001110 0000 1100 KRXX 0000 1100 0000 1000RR 0000 1010 kkkk Nord kkkk None KER None None kk C, D, ZO.N 2N 000000000000 000000000000 0000000000 0000000000 000000 000000000000 ODOB 0 000 000 0000 100 None 1001 None 1010 None ID None 1100 Ron 10 Non 1116 None 11 Nov none of the answers 10 illi 2 (5) TBLRD. TBLWT TBLWT+ TBLWT. TBLWT." Table Read with pre-increment Table Write Table Write with post-increment Table Write with post-decrement Table Write with pre-increment wou 0000 0000 0000 0000 0000 00000000 0000 00000000 0000 0000 0000 0000 00000000 0000 1010 None 2011 None 1100 None 1101 None 1110 None 1111 None a. none of the answers ob 12.6 milliseconds O c. 25.2 milliseconds Od 50.4 microseconds O e. 25.2 microseconds O f. 12.6 mircoseconds O g. 50.4 milliseconds