Question 7 i) Design a 'One-Hot Code' based Finite State Machine (FSM) circuit, that outputs a pulse (OP), of one clock cycle, after it has detected a single occurrence of 101110 on a input signal (IP) (the Most Significant Bit is the first input bit). The FSM then immediately resets and recommences monitoring for the next valid input sequence. The design should incorporate the appropriate initialization input signal on start up. (21 marks) i) Show the 'states' and the output waveform of the design for an input sequence (4 marks) Total marks: 25] of 1011011101