Question 7 The following synchronous circuit is composed of two D-Fup Flops and a small piece of combinational logic: F D-FF D-FF D Q D Q Qo Q CLK Qo+ G F Assuming Qo+ and Q1+ are the (D) inputs to the left and right flip-flops, respectively, fill out the following state table for the circuit above: Q1 Q0 Q1+ [Q100] [2000] [GOI [FO [Q101] [2001] [G] [FL] [Q110] [2010] [G2] [F2] 0 0 0 1 1 0 1 1 IQINI) 10011] [63] [F3]