Question No. 2 (10+10-20 points) Assume pipeline has 5-stages (FI, DI, RO, EI, wo), each stage takes one clock cycle, and WO stage for memory access only. For the following instructions to be executed in a pipeline, i. draw pipeline diagram if memory is single port. ii. draw pipeline diagram again, assuming assembler can re-arrange the instructions, memory is two-port, and execution stage takes two clock cycles MOV R2, [BX] MOV Ri, [CX] MOV R3, [AX] ADD RI, R SUB R2 R DEC R INC R3 sHep 485 hus daku Question No. 2 (10+10-20 points) Assume pipeline has 5-stages (FI, DI, RO, EI, wo), each stage takes one clock cycle, and WO stage for memory access only. For the following instructions to be executed in a pipeline, i. draw pipeline diagram if memory is single port. ii. draw pipeline diagram again, assuming assembler can re-arrange the instructions, memory is two-port, and execution stage takes two clock cycles MOV R2, [BX] MOV Ri, [CX] MOV R3, [AX] ADD RI, R SUB R2 R DEC R INC R3 sHep 485 hus daku