Question2 : Suppose you are given a non-pipelined processor design which has a cycle time of 10ns.

1) What is the best speedup you can get by pipelining it into 5 stages?

2) If the 5 stages are 1ns, 2ns, 4ns, 2ns, and 1ns, what is the maximum speedup you can achieve?

3) Follow up with point 2) - If each pipeline stage added also adds 20ps due to pipeline register delay, what is the maximum speedup you can achieve?