Questions below are based on this example CPU. The case study is also available in Lecture folder of study Material. (Let us name this CPU as UCS2011 for convenience of reference)

1. The JC62 has 7 machine instructions in its Instruction Set (LDA addr, STA addr, ADD, SUB, MBA, JMP addr, JN addr). Its hardware includes PC, IR, ALU, two registers AC and B, MAR, MDR, and a Control Unit. The datapath control in the CPU is achieved through 16 different control signals connected to various hardware components. Given below are Boolean expression for two of these 16 controls for designing a Hardwired Control unit:

W (memory write) = T5 * STA

R (memory read) = T1 + T4 * LDA

Where + means logical OR and * means logical AND

Write such Boolean expressions for LD, ED, EI and LI control signals. Also, design the Hardwired Unit for above four control signals using basic logic gates.

2. Write Microinstructions for machine instruction in the Instruction Set i.e. LDA addr, STA addr, and JN addr of UCS2011 machine.

3. Suppose, you as designer of the CPU decide to add two general-purpose registers named as D and E having two-way connection with the internal bus of the CPU. Draw the modified CPU diagram with these two registers.

4. Further suppose that you decide to enrich the Instruction Set (IS) with following instructions:

Instruction	Meaning	Action	Microsteps involved
MAD	Copy contents of D to AC	AC D
MDA	Copy contents of AC to D	D AC
MBE	Copy contents of E to B	B E
LDE addr	Load E register from the given address	E RAM[addr]

1. Fill the Microsteps column of this table
2. What additional control signals will be required for registers D and E taking the enriched IS into account.
3. Write the Boolean expressions for the additional control signals.
4. Develop the microcode for the four extra machine instructions given in the table above.

5. Translate the high-level assignment statement, x = x + y; for the example CPU as per its Instruction Set (consisting of 7 machine instructions). Assume that x and y are 12 bit integer variables available in system RAM at locations F0 and F1 respectively.

6. How many machine instructions your above-translated program has? Calculate the total number of clocks that the program will take to execute (including fetching action). Can you suggest an instruction which if added to the IS of the CPU will help in reducing the total instruction count of the translated program.

7. Relate answer of Q6 to the performance of a CPU. Recall that the execution time for a CPU is given by (IPP x CPI)/Clock rate, where IPP = number of instructions in a program; CPI = average number of clocks required per instruction.

8. For Q6, develop the microcode for the additional instructions suggested by you. Note that some additional/modified control signals may be required. Explain the same.

9. Translate the high-level assignment statements, for the example CPU as per its Instruction Set (consisting of 7 machine instructions). Write machine code for the translated statements assuming they are saved from address A0H.

while(x

z=z+x;

x=x+w;

}

Assume that w, x, y and z are 12 bit integer variables available in system RAM at locations F0, F1, F2 and F3 respectively where w=1, x=1, y=10 and z=0.