= R4; = R2; = a. Consider the following assembly language code: IO: ADDR4 R1 + RO; Il: SUB R9 R3 12: ADD R4 R5 + R6; I3: LDW R2 MEM(R3 + 100); I4: LDW R2 MEM(R2 + 0); 15: STW MEM(R4 + 100] 16: AND R2 R2 & Rl; 17: BEQ R 9 R1, Target; 18: AND R9 R9 & R1; Consider a pipeline with forwarding, hazard detection, and I delay slot for branches. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above code, complete the pipeline diagram below instructions on the left, cycles on top) for the code. Insert the characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that there two levels of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write-back stage writes to the register file. Label all data stalls (Draw an X in the box). Label all data forwards that the forwarding unit detects (arrow between the stages handing off the data and the stages receiving the data). What is the final execution time of the code? Cycles 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I# 0 2 IO 11 12 13 14 15 16 17 18 b. Consider the following sequence of actual outcomes for a single static branch. T means the branch is taken. N means the branch is not taken. For this question, assume that this is the only branch in the program. Assume that we try to predict this sequence with a Branch History Table (BHT) using one-bit counters. The counters in the BHT are initialized to the N state. Which of the branches in this sequence would be mis-predicted? You may use this table for your answer: Branch outcome Pedictor state before prediction N Misprediction? T T T N T N T T T ZE N T T T N ZE