1. Consider the following assembly language code where there are 7 instructions numbered I0 to I6, consider a MIPS design: I0: ADD R4 = R1 + R0; I1: SUB R9 = R3 - R4; I2: ADD R4 = R5 + R6; I3: LDW R2 = MEM[R3 + 100]; I4: LDW R2 = MEM[R2 + 0]; I5: STW MEM[R4 + 100] = R2; I6: AND R2 = R2 & R1;

2. Assuming no data forwarding, draw the time sequence pipeline diagram and calculate the number of clock cycles needed to complete the whole sequence of instruction.
4. Assuming forwarding, draw the time sequence pipeline diagram and calculate the number of clock cycles needed to complete the whole sequence of instruction.

2. Rearrange the following code to avoid/reduce the stall clock cycles

add $3,$2,$1 lw $4,4($3) addi $6,$4,1 sub $8,$3,$1