Refer to the NAND and NOR latches shown in the figure. The inputs (P1, P2) for both latches are first made (0,1) and then, after a few seconds, made (1,1). the corresponding stable output (Q1.02) are: Dar 0. 0. (A) NAND: first (0.1) then (0.1) NOR: first (1.0) then (0,0) (B) NAND: first (1,0) then (10) NOR: first (1.0) then (1.0) (C) NAND: first (1.0) then (1.0) NOR: first (1.0) then (0,0) (D) NAND: first (1.0) then (1.1) NOR: first (0.1) then (0.1)