refer to the pipeline design with forwarding and (load-use) hazard detection, shown below, which supports execution any sequence of the following MIPS instructions: add, sub, and, or, slt, lw, and sw.

Consider the execution of the following code in this pipeline.

 lw $t1, 0($t2) #1 add $t1, $t1, $t3 #2 lw $t3, 0($t1) #3 add $t2, $t2, $t3 #4

b) Depending on the existence/type of data hazard, the Forwarding Unit controls the two MUXes, which selects the input to the ALU unit. The control signals should be 00 when there is no data hazard; 10 on a EX hazard where we want to forward the date from the EX/MEM interstage buffer; and 01 upon a MEM hazard where we want to forward the date from the MEM/WB interstage buffer.

How much data will be forwarded from the EX/MEM interstage buffer to execute the above sequence of instructions? How much data will be forwarded from the MEM/WB interstage buffer?