Rewrite table 5-6 given the changes below:

a) Change the instruction encoding from vertical format for the memory reference instructions and horizontal format for the register reference and YO instructions to just vertical format for all instructions. Give an opcode for every instruction.

b) Add instructions PUSH and POP to the instruction set of the processor in chapter 5.. Instruction PUSH stores either AC or E in the system Stack. Instruction POP retrieves the value of AC or E from the system Stack. Give the Execute Cycle for each one of these two instructions, i.e., list micro-operations and their corresponding control functions for each instruction.

c) Suppose that a system Stack is used for saving return addresses to main program in handling subroutine calls and interrupt routines. This is in contrast to the processor in chapter 5, where return addresses are saved in memory for handling subroutine calls and interrupt routines. Do the following:

Rewrite the Interrupt Cycle such that the system stack is used for saving return address to the main program. So give micro-operations and control functions for the revised Interrupt Cycle.

Also introduce a new instruction called instruction RETI. This instruction retrieves the return address to main program from the system stack and sets PC to that address and also turns on the interrupt by setting IEN to 1. Also give the Execute Cycle for the RETI instruction by listing its micro-operations and the corresponding control functions.

Similarly revise instruction BSA for handling subroutine calls such that the return address to the mail program is saved in the system stack, not in the memory. Rename instruction BSA as instruction CALL. Give Execute Cycle of the instruction CALL by listing its micro-operations and the corresponding control functions.

Introduce a new instruction called instruction RETS. This instruction retrieves the return address to the main program from the system stack and sets PC to that address. Also give the Execute Cycle for the RETS instruction by listing its micro-operations and the corresponding control functions.

Then, rewrite the following code using the new table. (The current code is based off of table 5-6)

TABLE 5-6 Control Functions and Microoperations for the Basic Computer Fetch RITO PC AR R'Ta: IR MLARI, PC PC 1 Decode R'T: Da,..., DT Decade IR(12-14) AR IR (0-11), I IR (15) DIT AR MLAR] Indirect Interrupt: ToTiTi(IEN)(FGI+ FGO): R-1 RTO AR 0, TR PC RTI MARI TR: PC+0 RT PC PC 1, LEN 0, R 0, SC -0 Memory-reference: DOT. DR MLAR AND DOTS AC ACA DR, SC 0 DIT DR MLAR] ADD D,T. AC AC DR, E -Cout, SC 0 DR MMAR] LDA. D2T DAT. AC DR SC -0 DT MARI AC, SC 0 STA BUN DAT PC AR, SC 4-0 DST.: MLAR) C, AR AR 1 BSA, D,TS PC+AR SC -0 DR MLARl ISZ. D6T. DR DR 1 DET MIAR) DR if (DR 0) then (PC PC 1), SC 0 Register-reference DTI T3 IR(i) Bi (i 0, 1, 2, 11) SC 0 AC rB rB10 E +0 AC -AC CMA rB9: r.BT: A C t-shr AC, AC(15) E, E AC(0) CIR. Bie: AC+-shl AC, AC(O) E, E. AC(15) BS: AC AC 1 INC rB4: If CAC(15) 0) then (PC PC 1) SPA B3: If CAC(15) 1) then (PC PC 1) SNA r.Bi: If (AC 0) then PC PC 1) rB. If (E 0) then (PC PC 1) SZE HLT rB Input-output: DIT, p (common to all input-output instructions) IR B, (i 6, 7, 8, 9, 10, 11) SC 0 INP pB11: AC (0-7) INPR, FGI. 0 OUT pB10 OUTR AC(0-7), FGO 0 pB9: If (FGI 1) then (PC 4-PC 1) SKI SKO pBs: If (FGO 1) then (PC -PC i) ION pB IEN+1 IOF pB6 IEN 0 TABLE 5-6 Control Functions and Microoperations for the Basic Computer Fetch RITO PC AR R'Ta: IR MLARI, PC PC 1 Decode R'T: Da,..., DT Decade IR(12-14) AR IR (0-11), I IR (15) DIT AR MLAR] Indirect Interrupt: ToTiTi(IEN)(FGI+ FGO): R-1 RTO AR 0, TR PC RTI MARI TR: PC+0 RT PC PC 1, LEN 0, R 0, SC -0 Memory-reference: DOT. DR MLAR AND DOTS AC ACA DR, SC 0 DIT DR MLAR] ADD D,T. AC AC DR, E -Cout, SC 0 DR MMAR] LDA. D2T DAT. AC DR SC -0 DT MARI AC, SC 0 STA BUN DAT PC AR, SC 4-0 DST.: MLAR) C, AR AR 1 BSA, D,TS PC+AR SC -0 DR MLARl ISZ. D6T. DR DR 1 DET MIAR) DR if (DR 0) then (PC PC 1), SC 0 Register-reference DTI T3 IR(i) Bi (i 0, 1, 2, 11) SC 0 AC rB rB10 E +0 AC -AC CMA rB9: r.BT: A C t-shr AC, AC(15) E, E AC(0) CIR. Bie: AC+-shl AC, AC(O) E, E. AC(15) BS: AC AC 1 INC rB4: If CAC(15) 0) then (PC PC 1) SPA B3: If CAC(15) 1) then (PC PC 1) SNA r.Bi: If (AC 0) then PC PC 1) rB. If (E 0) then (PC PC 1) SZE HLT rB Input-output: DIT, p (common to all input-output instructions) IR B, (i 6, 7, 8, 9, 10, 11) SC 0 INP pB11: AC (0-7) INPR, FGI. 0 OUT pB10 OUTR AC(0-7), FGO 0 pB9: If (FGI 1) then (PC 4-PC 1) SKI SKO pBs: If (FGO 1) then (PC -PC i) ION pB IEN+1 IOF pB6 IEN 0