RISCV Computer Architechture Consider a classical $5-$stage pipelined processor having IF$,$ ID$,$ EX$,$ M and

WB stages. Each stage, except the EX stage, takes one clock cycle to perform its desired

operation. The system has one integer ALU, one floating point unit $($having an adder and a

floating point multiplier$).$ The floating point unit has its own register file $(f0-f31.$ The integer

ALU takes $1$ clock cycle to execute the operation, while the floating point adder requires $3$

clock cycles and floating point multiplier requires $5$ clock cycles to perform the corresponding

operations. The pipeline is stalled, for the required number of cycles, when a floating point

operation is performed. Forwarding is implemented to resolve any data hazards. The following

program is executed by the processor.

a$)$ List all the hazards that will be encountered while executing the given program.

b$)$ Evaluate the number of clock cycles required to complete one iteration of the loop and show

the number of cycles taken by each instruction separately. Assume that the result of branch

instruction is available in the ID stage.