Select whether the listed item is a challenge A) only for MC designs, B) only for pipelined designs, C) for both, D) for neither. Area, power, and critical path overheads due to saving state between cycles [ Choose ] Indivisible hardware resources with [ Choose ] higher latencies than other resources Fraction of workload consisting of [ Choose ] instructions that use more resources Instructions that read and write to [ Choose ] the same register Supporting complex instructions with variable behavior (e.g. REP prefix in [ Choose ] x86) Producer-consumer dependencies [ Choose ] among multiple instructions Low resource duty cycle when many [ Choose ] distinct resources are present